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Color TFT LCD Driver
MN838850
Source Driver for LCD Panel Drive
I Overview
The MN838850 converts digital display data from a personal computer or an engineering workstation to analog signal voltages to allow those signals to be displayed on a color TFT LCD panel.
I Features
* Includes a built-in D/A converter and accepts 8-bit digital input data for 16.7-million color display. * Output dynamic range: 14.6 V P-P (when AVDD = 15 V) * Supports both dot inversion drive and source inversion drive schemes. * Number of drive outputs: 384 * Input data bus: acquires two pixels at the same time * Supports control of data inversion at each clock cycle. * Supports correction. * Adopts a drive scheme that does not require precharging. * Allows serial cascade connection. * The clock is automatically stopped after the acquisition of a fixed amount of data. * The shift register shift direction can be set to be either left-to-right or right-to-left. * Digital circuit block features low-voltage operation: 2.7 to 3.6 V * Maximum operating clock frequency: 50 MHz (3.1 to 3.6 V), 40 MHz (2.7 to 3.6 V)
I Applications
* TFT LCD panels
Publication date: May 2002
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I Block Diagram
Y383 Y384
Y1
Y2
AVDD AVSS
Y3
Output Circuit
VREF0 to 9
10 D/A Converter 2
POL VOPU, VOPL
8
8
8
8
8
A
Two-line 384 x 8-bit latch
8
8
8
8
8
8
D00 to D07 D10 to D17 D20 to D27 D30 to D37 D40 to D47 D50 to D57 INV1 INV2
8 8 8 8 8 Latch 8
8 8 8 8 8 8
PLSR PRSL
Shift Register
DVDD
2
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DVSS
TEST
FY
RL
MN838850
I Pin Arrangement
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 30 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 PRSL D57 D56 D55 D54 D53 D52 D51 D50 D47 D46 D45 D44 D43 D42 D41 D40 D37 D36 D35 D34 D33 D32 D31 D30 DVDD TEST RL VOPU VREF9 VREF8 VREF7 VREF6 VREF5 AVDD AVSS VREF4 VREF3 VREF2 VREF1 VREF0 VOPL DVSS FY A POL INV2 INV1 D27 D26 D25 D24 D23 D22 D21 D20 D17 D16 D15 D14 D13 D12 D11 D10 D07 D06 D05 D04 D03 D02 D01 D00 PLSR Y384 Y383 Y382 Y381 Y380 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Y5 Y4 Y3 Y2 Y1
Cu Foil Surface Top View
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I Pin Descriptions
Pin No. D00 to D07 D10 to D17 D20 to D27 D30 to D37 D40 to D47 D50 to D57 Y1 to Y384 PLSR PRSL O I/O Image signal output Start pulse input and output I/O I Pin Name Image data input Description Image data input pins. The R, G, and B image signals are input using these pins. D07, D17, D27, D37, D47, D57 : MSB D00, D10, D20, D30, D40, D50 : LSB Analog image signal output pins. Internal shift register start pulse input and output pins. RL = "H" PLSR PRSL RL I Shift direction selection signal input Clock input Analog output control Output polarity reversal control input Data inversion control input Right shift input Right shift output RL = "L" Left shift output Left shift input
Input signal that selects the shift direction. High: Right shift (Y1 to Y384) Low: Left shift (Y384 to Y1) Data acquisition clock input pin. Controls the analog voltage output. Switches the reference voltage for odd and even outputs. Controls inversion of the input image signal. INV1: Used for D2(7 : 0), D1(7 : 0), D0(7 : 0) INV2: Used for D5(7 : 0), D4(7 : 0), D3(7 : 0) Inputs the correction voltage used by the D/A converter. Provides the reference voltage that determines the analog circuit operating point. VOPU: Reference voltage for the high side output VOPL : Reference voltage for the low side output
FY A POL INV1 INV2 VREF0 to 9 VOPU, VOPL
I I I I
I I
correction voltage input Analog reference voltage
AVDD AVSS DVDD DVSS TEST
I I I
Analog system power supply Digital system power supply Test (Pull-down resistor: 100 k)
Provides the power for the analog circuits. Provides the power for the digital circuits. Used for device testing. This pin must be left open during normal operation.
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I Functional Description
* Relationship between the data input and the analog output pins The input mode used by this IC is a two-pixel mode in which the data for two pixels is input in parallel from the D0(7:0), D1(7:0), D2(7:0), D3(7:0), D4(7:0), and D5(7:0) input ports. The correspondence between the data input ports and the output pins is as follows. Y(6n-5) = D00 to D07 Y(6n-2) = D30 to D37 Y(6n-4) = D10 to D17 Y(6n-3) = D20 to D27 Y(6n-1) = D40 to D47 Y(6n) = D50 to D57 (n = 1, 2, ******, 64)
Figure 1 shows an example of color data and pin connections when RL is high. This example shows the case where the pixels are in the order R, B, G starting at the left edge of the LCD panel.
R2n-1 B2n-1 G2n-1 R2n B2n G2n (n=1..)
D00 to D07 D10 to D17 D20 to D27 D30 to D37 D40 to D47 D50 to D57
Y10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
MN838850
************
R1 R1
B1 B1
G1 G1
R2 R2
B2 B2
G2 G2
R3 R3
B3 B3
G3 G3
R4 R4
*** ***
R1
B1
G1
R2
B2
G2
R3
B3
G3
R4
***
LCD Panel
FY
D0(7 : 0) D1(7 : 0) D2(7 : 0) D3(7 : 0) D4(7 : 0) D5(7 : 0)
R1 B1 G1 R2 B2 G2
R3 B3 G3 R4 B4 G4
R5 B5 G5 R6 B6 G6
R7 B7 G7 R8 B8
R9 B9 G9
R11 R13 R15 R17 R19 R21 R23 R25 R27 B11 B13 B15 B17 B19 B21 B23 B25 B27 G11 G13 G15 G17 G19 G21 G23 G25 G27
R10 R12 R14 R16 R18 R20 R22 R24 R26 R28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28
G8 G10 G12 G14 G16 G18 G20 G22 G24 G26 G28
Figure 1 Relationship between Input and Output Pins (When RL is high and the shift direction is Y1 to Y384)
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I Functional Description (continued)
* Relationship between the data input and the analog output pins (continued) The following presents the case with the same LCD panel color arrangement as figure 1 but with RL low. In figure 2, R1 corresponds to Y384, B1 to Y383, and G1 to Y382. Note that the relationship between the color data and the data ports here differs from that in figure 1.
LCD Panel
R1 B1 G1 R2 B2 G2 R3 B3 G3 R4
***
R1
B1
G1
R2
B2
G2
R3
B3
G3
R4
*** *********
Y384
Y383
Y382
Y381
Y380
Y379
Y378
Y377
R2n-1 B2n-1 G2n-1 R2n B2n G2n (n=1..) FY
D50 to D57 D40 to D47 D30 to D37 D20 to D27 D10 to D17 D00 to D07 MN838850
D0(7 : 0) D1(7 : 0) D2(7 : 0) D3(7 : 0) D4(7 : 0) D5(7 : 0)
G2 B2 R2 G1 B1 R1
G4 B4 R4 G3 B3 R3
G6 B6 R6 G5 B5 R5
G8 G10 G12 G14 G16 G18 G20 G22 G24 G26 G28 B8 R8 G7 B7 R7 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 R10 R12 R14 R16 R18 R20 R22 R24 R26 R28 G9 B9 R9 G11 G13 G15 G17 G19 G21 G23 G25 G27 B11 B13 B15 B17 B19 B21 B23 B25 B27 R11 R13 R15 R17 R19 R21 R23 R25 R27
Figure 2 Relationship between Input and Output Pins (When RL is low and the shift direction is Y384 to Y1)
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Y376
Y377
MN838850
I Functional Description (continued)
* Dot inversion drive Since dot inversion drive is used, the analog output voltages with respect to the opposite electrode voltage differ in polarity for each of the odd and even numbered output pins. This output voltage polarity is controlled by POL. The table below lists the correspondence between the POL polarity setting, the analog output polarity and the VREF used. POL "L" "H" Y2n-1 Y2n
Positive polarity Negativepolarity VREF9 to 5 VREF4 to 0 Negativepolarity Positive polarity VREF4 to 0 VREF9 to 5
The POL switching timing is presented below. POL should be switched during the period when A is low, after the last data has been input, and before the next start signal has been input. The POL signal level is acquired by the device internally on the falling edge of the A signal. The output polarity is determined by the acquired signal level.
A
POL Negative polarity Y2n-1 Y2n (n=1 to 192) One horizontal period Positive polarity
Positive polarity Negative polarity
Negative polarity Positive polarity Opposite electrode voltages
POL Switching Timing
A Start Signal First data Dxx Last data POL One horizontal period Details of the POL Switching Timing Last data First data
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I Functional Description (continued)
* Dot inversion drive (continued) Next we describe dot inversion drive operation. The symbol "+" here means a voltage that is positive with respect to the voltage on the opposite electrode, and "-" means a voltage that is negative with respect to the voltage on the opposite electrode. The figure below shows the dot inversion drive operation. Since POL is low in the first line of the first field, Y1 will be + and Y2 will be -, that is, odd-numbered output pins will have positive polarity and even-numbered output pins will have negative polarity. Since POL is switched to high for the second line, odd-numbered output pins will have negative polarity and evennumbered output pins will have positive polarity. Thereafter, the polarity of the output voltages is determined by the POL polarity. In the second field, the POL polarity will be the opposite of what it was for the first field, so the output voltage polarities will be reversed.
Y1
Y2
Y3
POL "L" "H" "L" "H"
Field 1
Line 1 Line 2 Line 3 Line 4
+ - + -
- + - + * * * * * *
+ - + -
Field 2
Line 1 Line 2 Line 3
- + -
+ - +
- + -
"H" "L" "H"
Note that if POL is inverted not every line, but only every field, the output polarities will be as shown below.
Y1
Y2
Y3
POL "L" "L" "L"
Field 1
Line 1 Line 2 Line 3
+ + +
- - - * * * * * *
+ + +
Field 2
Line 1 Line 2 Line 3
- - -
+ + +
- - -
"H" "H" "H"
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I Functional Description (continued)
* Operation when Connected in Cascade When RL is high: Driver A acquires the PLSR start pulse on the rising edge of FY and starts acquiring data on the next FY rising edge. The PRSL (carry) output will go high 64 clock pulses after the start pulse input and data acquisition will stop one clock cycle later. Driver B receives the driver A PRSL rising edge and starts accepting data one clock cycle later.
64 clock cycles FY
Acquired on the falling edge of FY.
State of signal 1 State of signal 2 Driver B D00 to D07 D10 to D17 D20 to D27 D30 to D37 D40 to D47 D50 to D57 1 3 5 *** 125 127 129 1 130 2 131 3 132 4 133 5 134 6
2
4
6
***
126
128
Data acquired by driver A
LCD controller 8-bit RGB data
1 PLSR Start pulse Driver A PRSL
2 PLSR PRSL PLSR PRSL Driver B Driver C
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I Functional Description (continued)
* Relationship between input data values and output voltages The IC outputs voltages with discrete values and differing polarities for the odd and even output pins with respect to the common electrode. The output voltage is determined by the input data value, the correction voltages (VREF0 to VREF9), VOPL, VOPU, and POL.
AVDD
AVDD
Output Voltage
Common voltage
Common voltage
00
1F
3F
5F
7F
9F
BF
DF
FF
Output Voltage
00
1F
3F
5F
7F
9F
BF
DF
FF
Input data
Input data (Hexadecimal)
Input data
Relationship between Input Data and Output Voltage (VREF0 > VREF1 > VREF2 > VREF3 > VREF4, VREF5 > VREF6 > VREF7 > VREF8 > VREF9)
Relationship between Input Data and Output Voltage (VREF0 < VREF1 < VREF2 < VREF3 < VREF4, VREF5 < VREF6 < VREF7 < VREF8 < VREF9)
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I Functional Description (continued)
* Relationship between input data values and output voltages (continued) Apply the voltages for the correction to the pins VREF0 to VREF9. The correction voltage input pins are divided into two groups: the high-level output control group and the low-level output control group, and each group is connected in series with resistors. Each of these resistor series has a total typical value of 14 k. This structure is shown in the figure. The typical values of the resistors are shown in parentheses. Note that since these voltages are resistor divided internally, the voltages applied to the VREF pins should be applied through a low-impedance circuit. If the voltages are directly applied by the resistor divider, the desired output voltages may not result. IC internal circuits VREF9 R0 (2000 ) R1 (3800 ) Data correspondence High-level FF output side
VREF8
External reference voltage generating circuit
VREF7 R2 (4500 ) R3 (3700 ) 00 Low-level 00 output side
VREF6
VREF5 VREF4
VREF3
R4 (3700 ) R5 (4500 ) R6 (3800 ) R7 (2000 )
VREF2
VREF1
VREF0
FF
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I Functional Description (continued)
* Table 1 Relationship between VREF Voltages and Analog Output Voltages (High-level side) (Values are examples) VREF5 = 9.200, VREF6 = 10.635, VREF7 = 12.380, VREF8 = 13.854, VREF9 = 14.630, VOPU = 11.250 Display data 00 01 02 * * * 0D 0E 0F 10 11 12 * * * 1D 1E 1F 20 21 22 * * * 2D 2E 2F 30 31 32 * * * 3D 3E 3F 40 41 42 * * * 4D 4E 4F Logical expression VOPU x 63/31- (42 x VREF8+1238 x VREF9) /1240 VOPU x 63/31- (84 x VREF8+1196 x VREF9) /1240 VOPU x 63/31- (126 x VREF8+1154 x VREF9) /1240 VOPU x 63/31- (588 x VREF8+692 x VREF9) /1240 VOPU x 63/31- (630 x VREF8+650 x VREF9) /1240 VOPU x 63/31- (672 x VREF8+608 x VREF9) /1240 VOPU x 63/31- (710 x VREF8+570 x VREF9) /1240 VOPU x 63/31- (748 x VREF8+532 x VREF9) /1240 VOPU x 63/31- (786 x VREF8+494 x VREF9) /1240 VOPU x 63/31- (1204 x VREF8+76 x VREF9) /1240 VOPU x 63/31- (1242 x VREF8+38 x VREF9) /1240 VOPU x 63/31- (1280 x VREF8+0 x VREF9) /1240 VOPU x 63/31- (32 x VREF7+2400 x VREF8) /2356 VOPU x 63/31- (64 x VREF7+2368 x VREF8) /2356 VOPU x 63/31- (96 x VREF7+2336 x VREF8) /2356 VOPU x 63/31- (448 x VREF7+1984 x VREF8) /2356 VOPU x 63/31- (480 x VREF7+1952 x VREF8) /2356 VOPU x 63/31- (512 x VREF7+1920 x VREF8) /2356 VOPU x 63/31- (538 x VREF7+1894 x VREF8) /2356 VOPU x 63/31- (564 x VREF7+1868 x VREF8) /2356 VOPU x 63/31- (590 x VREF7+1842 x VREF8) /2356 VOPU x 63/31- (876 x VREF7+1556 x VREF8) /2356 VOPU x 63/31- (902 x VREF7+1530 x VREF8) /2356 VOPU x 63/31- (928 x VREF7+1504 x VREF8) /2356 VOPU x 63/31- (953 x VREF7+1479 x VREF8) /2356 VOPU x 63/31- (978 x VREF7+1454 x VREF8) /2356 VOPU x 63/31- (1003 x VREF7+1429 x VREF8) /2356 VOPU x 63/31- (1278 x VREF7+1154 x VREF8) /2356 VOPU x 63/31- (1303 x VREF7+1129 x VREF8) /2356 VOPU x 63/31- (1328 x VREF7+1104 x VREF8) /2356 Voltage level 7.787 7.813 7.839 8.128 8.155 8.181 8.205 8.228 8.252 8.514 8.537 8.561 8.581 8.601 8.621 8.841 8.861 8.882 8.898 8.914 8.930 9.109 9.125 9.142 9.157 9.173 9.189 9.361 9.376 9.392 Voltage level difference 0.026 0.026 0.026 0.026 0.026 0.023 0.023 0.023 0.023 0.023 0.023 0.020 0.020 0.020 0.020 0.020 0.020 0.016 0.016 0.016 0.016 0.016 0.016 0.015 0.015 0.015 0.015 0.015 0.015 0.015
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I Functional Description (continued)
* Table 1 (continued) Relationship between VREF Voltages and Analog Output Voltages (High-level side) (Values are examples) VREF5 = 9.200, VREF6 = 10.635, VREF7 = 12.380, VREF8 = 13.854, VREF9 = 14.630, VOPU = 11.250 Display data 50 51 52 * * * 5D 5E 5F 60 61 62 * * * 6D 6E 6F 70 71 72 * * * 7D 7E 7F 80 81 82 * * * 8D 8E 8F 90 91 92 * * * 9D 9E 9F Logical expression VOPU x 63/31- (1353 x VREF7+1079 x VREF8) /2356 VOPU x 63/31- (1378 x VREF7+1054 x VREF8) /2356 VOPU x 63/31- (1403 x VREF7+1029 x VREF8) /2356 VOPU x 63/31- (1678 x VREF7+754 x VREF8) /2356 VOPU x 63/31- (1703 x VREF7+729 x VREF8) /2356 VOPU x 63/31- (1728 x VREF7+704 x VREF8) /2356 VOPU x 63/31- (1750 x VREF7+682 x VREF8) /2356 VOPU x 63/31- (1772 x VREF7+660 x VREF8) /2356 VOPU x 63/31- (1794 x VREF7+638 x VREF8) /2356 VOPU x 63/31- (2036 x VREF7+396 x VREF8) /2356 VOPU x 63/31- (2058 x VREF7+374 x VREF8) /2356 VOPU x 63/31- (2080 x VREF7+352 x VREF8) /2356 VOPU x 63/31- (2102 x VREF7+330 x VREF8) /2356 VOPU x 63/31- (2124 x VREF7+308 x VREF8) /2356 VOPU x 63/31- (2146 x VREF7+286 x VREF8) /2356 VOPU x 63/31- (2388 x VREF7+44 x VREF8) /2356 VOPU x 63/31- (2410 x VREF7+22 x VREF8) /2356 VOPU x 63/31- (2432 x VREF7+0 x VREF8) /2356 VOPU x 63/31- (11 x VREF6+1429 x VREF7) /1395 VOPU x 63/31- (22 x VREF6+1418 x VREF7) /1395 VOPU x 63/31- (33 x VREF6+1407 x VREF7) /1395 VOPU x 63/31- (154 x VREF6+1286 x VREF7) /1395 VOPU x 63/31- (165 x VREF6+1275 x VREF7) /1395 VOPU x 63/31- (176 x VREF6+1264 x VREF7) /1395 VOPU x 63/31- (187 x VREF6+1253 x VREF7) /1395 VOPU x 63/31- (198 x VREF6+1242 x VREF7) /1395 VOPU x 63/31- (209 x VREF6+1231 x VREF7) /1395 VOPU x 63/31- (330 x VREF6+1110 x VREF7) /1395 VOPU x 63/31- (341 x VREF6+1099 x VREF7) /1395 VOPU x 63/31- (352 x VREF6+1088 x VREF7) /1395 Voltage level 9.408 9.423 9.439 9.611 9.627 9.642 9.656 9.670 9.683 9.835 9.849 9.862 9.876 9.890 9.904 10.055 10.069 10.083 10.096 10.110 10.124 10.275 10.289 10.303 10.317 10.330 10.344 10.495 10.509 10.523 Voltage level difference 0.015 0.015 0.015 0.015 0.015 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.016
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I Functional Description (continued)
* Table 1 (continued) Relationship between VREF Voltages and Analog Output Voltages (High-level side) (Values are examples) VREF5 = 9.200, VREF6 = 10.635, VREF7 = 12.380, VREF8 = 13.854, VREF9 = 14.630, VOPU = 11.250 Display data A0 A1 A2 * * * AD AE AF B0 B1 B2 * * * BD BE BF C0 C1 C2 * * * CD CE CF D0 D1 D2 * * * DD DE DF E0 E1 E2 * * * ED EE EF Logical expression VOPU x 63/31- (365 x VREF6+1075 x VREF7) /1395 VOPU x 63/31- (378 x VREF6+1062 x VREF7) /1395 VOPU x 63/31- (391 x VREF6+1049 x VREF7) /1395 VOPU x 63/31- (534 x VREF6+906 x VREF7) /1395 VOPU x 63/31- (547 x VREF6+893 x VREF7) /1395 VOPU x 63/31- (560 x VREF6+880 x VREF7) /1395 VOPU x 63/31- (573 x VREF6+867 x VREF7) /1395 VOPU x 63/31- (586 x VREF6+854 x VREF7) /1395 VOPU x 63/31- (599 x VREF6+841 x VREF7) /1395 VOPU x 63/31- (742 x VREF6+698 x VREF7) /1395 VOPU x 63/31- (755 x VREF6+685 x VREF7) /1395 VOPU x 63/31- (768 x VREF6+672 x VREF7) /1395 VOPU x 63/31- (786 x VREF6+654 x VREF7) /1395 VOPU x 63/31- (804 x VREF6+636 x VREF7) /1395 VOPU x 63/31- (822 x VREF6+618 x VREF7) /1395 VOPU x 63/31- (1020 x VREF6+420 x VREF7) /1395 VOPU x 63/31- (1038 x VREF6+402 x VREF7) /1395 VOPU x 63/31- (1056 x VREF6+384 x VREF7) /1395 VOPU x 63/31- (1080 x VREF6+360 x VREF7) /1395 VOPU x 63/31- (1104 x VREF6+336 x VREF7) /1395 VOPU x 63/31- (1128 x VREF6+312 x VREF7) /1395 VOPU x 63/31- (1392 x VREF6+48 x VREF7) /1395 VOPU x 63/31- (1416 x VREF6+24 x VREF7) /1395 VOPU x 63/31- (1440 x VREF6+0 x VREF7) /1395 VOPU x 63/31- (66 x VREF5+2302 x VREF6) /2294 VOPU x 63/31- (132 x VREF5+2236 x VREF6) /2294 VOPU x 63/31- (198 x VREF5+2170 x VREF6) /2294 VOPU x 63/31- (924 x VREF5+1444 x VREF6) /2294 VOPU x 63/31- (990 x VREF5+1378 x VREF6) /2294 VOPU x 63/31- (1056 x VREF5+1312 x VREF6) /2294 Voltage level 10.539 10.556 10.572 10.751 10.767 10.783 10.800 10.816 10.832 11.011 11.027 11.043 11.066 11.089 11.111 11.359 11.381 11.404 11.434 11.464 11.494 11.824 11.854 11.884 11.926 11.967 12.008 12.462 12.504 12.545 Voltage level difference 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.022 0.022 0.022 0.022 0.022 0.022 0.030 0.030 0.030 0.030 0.030 0.030 0.041 0.041 0.041 0.041 0.041 0.041 0.051
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I Functional Description (continued)
* Table 1 (continued) Relationship between VREF Voltages and Analog Output Voltages (High-level side) (Values are examples) VREF5 = 9.200, VREF6 = 10.635, VREF7 = 12.380, VREF8 = 13.854, VREF9 = 14.630, VOPU = 11.250 Display data F0 F1 F2 * * * FD FE FF Logical expression VOPU x 63/31- (1138 x VREF5+1230 x VREF6) /2294 VOPU x 63/31- (1220 x VREF5+1148 x VREF6) /2294 VOPU x 63/31- (1302 x VREF5+1066 x VREF6) /2294 VOPU x 63/31- (2204 x VREF5+164 x VREF6) /2294 VOPU x 63/31- (2286 x VREF5+82 x VREF6) /2294 VOPU x 63/31- (2368 x VREF5+0 x VREF6) /2294 Voltage level 12.596 12.647 12.699 13.263 13.314 13.366 Voltage level difference 0.051 0.051 0.051 0.051 0.051
* Table 2 Relationship between VREF Voltages and Analog Output Voltages (Low-level side) (Values are examples) VREF0 = 1.760, VREF1 = 2.536, VREF2 = 4.010, VREF3 = 5.755, VREF4 = 7.190, VOPL = 3.750 Display data 00 01 02 * * * 0D 0E 0F 10 11 12 * * * 1D 1E 1F 20 21 22 * * * 2D 2E 2F Logical expression VOPL x 63/31- (42 x VREF1+1238 x VREF0) /1240 VOPL x 63/31- (84 x VREF1+1196 x VREF0) /1240 VOPL x 63/31- (126 x VREF1+1154 x VREF0) /1240 VOPL x 63/31- (588 x VREF1+692 x VREF0) /1240 VOPL x 63/31- (630 x VREF1+650 x VREF0) /1240 VOPL x 63/31- (672 x VREF1+608 x VREF0) /1240 VOPL x 63/31- (710 x VREF1+570 x VREF0) /1240 VOPL x 63/31- (748 x VREF1+532 x VREF0) /1240 VOPL x 63/31- (786 x VREF1+494 x VREF0) /1240 VOPL x 63/31- (1204 x VREF1+76 x VREF0) /1240 VOPL x 63/31- (1242 x VREF1+38 x VREF0) /1240 VOPL x 63/31- (1280 x VREF1+0 x VREF0) /1240 VOPL x 63/31- (32 x VREF2+2400 x VREF1) /2356 VOPL x 63/31- (64 x VREF2+2368 x VREF1) /2356 VOPL x 63/31- (96 x VREF2+2336 x VREF1) /2356 VOPL x 63/31- (448 x VREF2+1984 x VREF1) /2356 VOPL x 63/31- (480 x VREF2+1952 x VREF1) /2356 VOPL x 63/31- (512 x VREF2+1920 x VREF1) /2356 Voltage level 5.777 5.751 5.725 5.436 5.410 5.383 5.360 5.336 5.312 5.051 5.027 5.003 4.983 4.963 4.943 4.723 4.703 4.683 Voltage level difference 0.026 0.026 0.026 0.026 0.026 0.023 0.023 0.023 0.023 0.023 0.023 0.020 0.020 0.020 0.020 0.020 0.020 0.016
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I Functional Description (continued)
* Table 2 (continued) Relationship between VREF Voltages and Analog Output Voltages (Low-level side) (Values are examples) VREF0 = 1.760, VREF1 = 2.536, VREF2 = 4.010, VREF3 = 5.755, VREF4 = 7.190, VOPL = 3.750 Display data 30 31 32 * * * 3D 3E 3F 40 41 42 * * * 4D 4E 4F 50 51 52 * * * 5D 5E 5F 60 61 62 * * * 6D 6E 6F 70 71 72 * * * 7D 7E 7F Logical expression VOPL x 63/31- (538 x VREF2+1894 x VREF1) /2356 VOPL x 63/31- (564 x VREF2+1868 x VREF1) /2356 VOPL x 63/31- (590 x VREF2+1842 x VREF1) /2356 VOPL x 63/31- (876 x VREF2+1556 x VREF1) /2356 VOPL x 63/31- (902 x VREF2+1530 x VREF1) /2356 VOPL x 63/31- (928 x VREF2+1504 x VREF1) /2356 VOPL x 63/31- (953 x VREF2+1479 x VREF1) /2356 VOPL x 63/31- (978 x VREF2+1454 x VREF1) /2356 VOPL x 63/31- (1003 x VREF2+1429 x VREF1) /2356 VOPL x 63/31- (1278 x VREF2+1154 x VREF1) /2356 VOPL x 63/31- (1303 x VREF2+1129 x VREF1) /2356 VOPL x 63/31- (1328 x VREF2+1104 x VREF1) /2356 VOPL x 63/31- (1353 x VREF2+1079 x VREF1) /2356 VOPL x 63/31- (1378 x VREF2+1054 x VREF1) /2356 VOPL x 63/31- (1403 x VREF2+1029 x VREF1) /2356 VOPL x 63/31- (1678 x VREF2+754 x VREF1) /2356 VOPL x 63/31- (1703 x VREF2+729 x VREF1) /2356 VOPL x 63/31- (1728 x VREF2+704 x VREF1) /2356 VOPL x 63/31- (1750 x VREF2+682 x VREF1) /2356 VOPL x 63/31- (1772 x VREF2+660 x VREF1) /2356 VOPL x 63/31- (1794 x VREF2+638 x VREF1) /2356 VOPL x 63/31- (2036 x VREF2+396 x VREF1) /2356 VOPL x 63/31- (2058 x VREF2+374 x VREF1) /2356 VOPL x 63/31- (2080 x VREF2+352 x VREF1) /2356 VOPL x 63/31- (2102 x VREF2+330 x VREF1) /2356 VOPL x 63/31- (2124 x VREF2+308 x VREF1) /2356 VOPL x 63/31- (2146 x VREF2+286 x VREF1) /2356 VOPL x 63/31- (2388 x VREF2+44 x VREF1) /2356 VOPL x 63/31- (2410 x VREF2+22 x VREF1) /2356 VOPL x 63/31- (2432 x VREF2+0 x VREF1) /2356 Voltage level 4.666 4.650 4.634 4.455 4.439 4.422 4.407 4.391 4.376 4.203 4.188 4.172 4.157 4.141 4.125 3.953 3.938 3.922 3.908 3.894 3.881 3.729 3.716 3.702 3.688 3.674 3.660 3.509 3.495 3.482 Voltage level difference 0.016 0.016 0.016 0.016 0.016 0.015 0.015 0.015 0.015 0.015 0.015 0.015 0.015 0.015 0.015 0.015 0.015 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013
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MN838850
I Functional Description (continued)
* Table 2 (continued) Relationship between VREF Voltages and Analog Output Voltages (Low-level side) (Values are examples) VREF0 = 1.760, VREF1 = 2.536, VREF2 = 4.010, VREF3 = 5.755, VREF4 = 7.190, VOPL = 3.750 Display data 80 81 82 * * * 8D 8E 8F 90 91 92 * * * 9D 9E 9F A0 A1 A2 * * * AD AE AF B0 B1 B2 * * * BD BE BF C0 C1 C2 * * * CD CE CF Logical expression VOPL x 63/31- (11 x VREF3+1429 x VREF2) /1395 VOPL x 63/31- (22 x VREF3+1418 x VREF2) /1395 VOPL x 63/31- (33 x VREF3+1407 x VREF2) /1395 VOPL x 63/31- (154 x VREF3+1286 x VREF2) /1395 VOPL x 63/31- (165 x VREF3+1275 x VREF2) /1395 VOPL x 63/31- (176 x VREF3+1264 x VREF2) /1395 VOPL x 63/31- (187 x VREF3+1253 x VREF2) /1395 VOPL x 63/31- (198 x VREF3+1242 x VREF2) /1395 VOPL x 63/31- (209 x VREF3+1231 x VREF2) /1395 VOPL x 63/31- (330 x VREF3+1110 x VREF2) /1395 VOPL x 63/31- (341 x VREF3+1099 x VREF2) /1395 VOPL x 63/31- (352 x VREF3+1088 x VREF2) /1395 VOPL x 63/31- (365 x VREF3+1075 x VREF2) /1395 VOPL x 63/31- (378 x VREF3+1062 x VREF2) /1395 VOPL x 63/31- (391 x VREF3+1049 x VREF2) /1395 VOPL x 63/31- (534 x VREF3+906 x VREF2) /1395 VOPL x 63/31- (547 x VREF3+893 x VREF2) /1395 VOPL x 63/31- (560 x VREF3+880 x VREF2) /1395 VOPL x 63/31- (573 x VREF3+867 x VREF2) /1395 VOPL x 63/31- (586 x VREF3+854 x VREF2) /1395 VOPL x 63/31- (599 x VREF3+841 x VREF2) /1395 VOPL x 63/31- (742 x VREF3+698 x VREF2) /1395 VOPL x 63/31- (755 x VREF3+685 x VREF2) /1395 VOPL x 63/31- (768 x VREF3+672 x VREF2) /1395 VOPL x 63/31- (786 x VREF3+654 x VREF2) /1395 VOPL x 63/31- (804 x VREF3+636 x VREF2) /1395 VOPL x 63/31- (822 x VREF3+618 x VREF2) /1395 VOPL x 63/31- (1020 x VREF3+420 x VREF2) /1395 VOPL x 63/31- (1038 x VREF3+402 x VREF2) /1395 VOPL x 63/31- (1056 x VREF3+384 x VREF2) /1395 Voltage level 3.468 3.454 3.440 Voltage level difference 0.013 0.013 0.013
3.289 3.275 3.261 3.248 3.234 3.220 3.069 3.055 3.041 3.025 3.009 2.992 2.813 2.797 2.781 2.765 2.748 2.732 2.553 2.537 2.521 2.498 2.476 2.453 2.205 2.183 2.160
0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.013 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.016 0.022 0.022 0.022 0.022 0.022 0.022 0.030
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I Functional Description (continued)
* Table 2 (continued) Relationship between VREF Voltages and Analog Output Voltages (Low-level side) (Values are examples) VREF0 = 1.760, VREF1 = 2.536, VREF2 = 4.010, VREF3 = 5.755, VREF4 = 7.190, VOPL = 3.750 Display data D0 D1 D2 * * * DD DE DF E0 E1 E2 * * * ED EE EF F0 F1 F2 * * * FD FE FF Logical expression VOPL x 63/31- (1080 x VREF3+360 x VREF2) /1395 VOPL x 63/31- (1104 x VREF3+336 x VREF2) /1395 VOPL x 63/31- (1128 x VREF3+312 x VREF2) /1395 VOPL x 63/31- (1392 x VREF3+48 x VREF2) /1395 VOPL x 63/31- (1416 x VREF3+24 x VREF2) /1395 VOPL x 63/31- (1440 x VREF3+0 x VREF2) /1395 VOPL x 63/31- (66 x VREF4+2302 x VREF3) /2294 VOPL x 63/31- (132 x VREF4+2236 x VREF3) /2294 VOPL x 63/31- (198 x VREF4+2170 x VREF3) /2294 VOPL x 63/31- (924 x VREF4+1444 x VREF3) /2294 VOPL x 63/31- (990 x VREF4+1378 x VREF3) /2294 VOPL x 63/31- (1056 x VREF4+1312 x VREF3) /2294 VOPL x 63/31- (1138 x VREF4+1230 x VREF3) /2294 VOPL x 63/31- (1220 x VREF4+1148 x VREF3) /2294 VOPL x 63/31- (1302 x VREF4+1066 x VREF3) /2294 VOPL x 63/31- (2204 x VREF4+164 x VREF3) /2294 VOPL x 63/31- (2286 x VREF4+82 x VREF3) /2294 VOPL x 63/31- (2368 x VREF4+0 x VREF3) /2294 Voltage level 2.130 2.100 2.070 1.740 1.710 1.680 1.639 1.597 1.556 1.102 1.061 1.019 0.968 0.917 0.865 0.301 0.250 0.199 Voltage level difference 0.030 0.030 0.030 0.030 0.030 0.041 0.041 0.041 0.041 0.041 0.041 0.051 0.051 0.051 0.051 0.051 0.051
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MN838850
I Functional Description (continued)
* Relationship between the A signal, the image input timing, and the start pulse The figure below shows the relationship between the A signal, the image data input timing, and the start pulse. The last data of the image should be input within one clock cycle of the fall of the A signal. Data input two or more clock cycles later will not be transmitted to the analog outputs and the IC will not be able to output the correct analog voltage. And also hold the levels of the data bus fixed from 1 s before the rise of the A signal until 4 clock cycles after the rise of the A signal. The output analog voltages may be displaced or shifted if the data bus levels are changed with that timing.
FY A signal Start pulse PLSR(RL = "H") PRSL(RL = "L") Data 1 clock cycle (max.) 4 clock cycle (min.) N-2 N-1 N Last data value 1 s(min.) Period during which the data must be held fixed 1 2 3 First data value
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I Functional Description (continued)
* Data inversion control function All the bits in the input image data can be inverted at the same time, thus creating new data values to be used by controlling the INV1 and INV2 pins. INV1 inverts the D0(7:0), D1(7:0), and D2(7:0) data and INV2 inverts the D3(7:0), D4(7:0), and D5(7:0) data. The figure below shows the inversion control provided by INV1 and INV2 for the input image data. The input image data and the INV1 and INV2 states are acquired on the same clock cycle, and the data is controlled by the INV1 and INV2 logic states at that time.
FY
D07 to 00 D17 to 10 D27 to 20 INV1 Internal data ID07 to 00 ID17 to 10 ID27 to 20
00 00 00
00 00 00
00 05 08
0F 0F 0F
FF FF FF
FF FE FD
FF FF FF
00 00 00
00 00 00
05 05 05
08 08 08
FF FF FF
00 00 00
FF FA F7
0F 0F 0F
FF FF FF
00 01 02
FF FF FF
00 00 00
00 00 00
05 05 05
08 08 08
Since INV1 is high, All the bits in the data D0x, D1x, and D2x are inverted.
FY
D37 to 30 D47 to 40 D57 to 50 INV2 Internal data ID37 to 30 ID47 to 40 ID57 to 50
00 00 00
00 00 00
0A 0C 0F
0F 0F 0F
FF FF FF
F7 F4 F1
FF FF FF
00 00 00
00 00 00
05 05 05
08 08 08
FF FF FF
00 00 00
F5 F3 F0
0F 0F 0F
FF FF FF
08 0B 0E
FF FF FF
00 00 00
00 00 00
05 05 05
08 08 08
Since INV1 is high, All the bits in the data D0x, D1x, and D2x are inverted.
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MN838850
I Functional Description (continued)
* Possible periods of the clock stop The possible periods of the clock stop in which clock has been stopped are shown below. The clock signal must be provided during the period starting one clock cycle before the start pulse input and ending 5 clock cycles after the rise of the A signal. However, if it is not the case that the first data is input with the next clock timing (T) after the input of the start pulse, the clock may be stopped during the period between the start pulse input and the start of data input. The clock signal may be stopped at either the high or low level.
FY Start pulse PLSR(RL = "H") PRSL(RL = "L") DXX
T
First data 1 3 *** N 1 2 3 4 5
Last data A signal
Period during which clock input is required Period during which clock input may be stopped
I Electrical Characteristics
1. Absolute Maximum Ratings at AVSS = 0 V, DVSS = 0 V Parameter Digital system supply voltage Analog system supply voltage Digital input voltage Analog input voltage Digital output voltage Analog output voltage Operating temperature Storage temperature Symbol DVDD AVDD VI1 VI2 VO1 VO2 Topr Tstg Rating - 0.3 to +7.0 - 0.3 to +17 - 0.3 to DVDD+0.3 - 0.3 to AVDD+0.3 - 0.3 to DVDD+0.3 - 0.3 to AVDD+0.3 -20 to +75 -40 to +110 Unit V V V V V V C C
Note) The absolute maximum ratings are limiting values under which the device will not be destroyed. Operation is not guaranteed within these ranges.
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I Electrical Characteristics (continued)
2. Operating Conditions at AVSS = DVSS = 0 V, Ta = -20 C to +75 C Parameter Operating digital system supply voltage Symbol DVDD Conditions fFY max = 50 MHz fFY max = 40 MHz Operating analog system supply voltage AVDD VREF 5 to 9 Operating frequency DVDD = 3.1 V to 3.6 V DVDD = 2.7 V to 3.6 V Digital signal input capacitance correction voltage input capacitance VOPL input voltage range VOPU input voltage range VREF resistance VREF9 to 5, VREF4 to 0 RVREF CIN CVREF At 1 MHz At 1 MHz correction voltage input voltage range VREF 0 to 4 Min 3.1 2.7 14.5 0.2 AVDD/2 AVDD/4 - 0.2 AVDD x 3/4- 0.2 Typ 5 500 14 Max 3.6 3.6 15.5 AVDD/2 AVDD- 0.2 50 40 AVDD/4 + 0.2 AVDD x 3/4+ 0.2 pF pF V V k MHz V V Unit V
Note) 1. All the AVDD power supply pins must be connected to each other directly. 2. All the AVSS and DVSS power supply pins must be connected to each other directly. 3. When first applying power, first apply the DVDD voltage, then apply the logic input pin signal levels, and then apply the A VDD voltage. After that apply the VOP and VREF reference voltages. When cutting the power, remove these voltages in the reverse order.
3. DC Characteristics at DVDD = 2.7 V to 3.6 V, AVDD = 14.5 V to 15.5 V, AVSS = DVSS = 0 V, Ta = -20 C to +75 C Parameter Operating analog supply current 1 *1,3 Operating analog supply current 2 Operating digital supply current *1,2 Digital quiescent supply current Symbol ISS1 ISS2 ISS3 ISS4 In the clock stopped state AVDD = 15 V *1, 3 With no load Conditions Min 0.7 x DVDD 0 -10 0.7 x DVDD 0 DVDD = 3.3 V, IO = -5 mA DVDD = 3.3 V, IO = 2 mA 0.7 x DVDD -10 Typ 39 11 2 Max 45 8 100 Unit mA mA mA A
1) Input pins RL, A, D00 to D07, D10 to D17, D20 to D27, D30 to D37, D40 to D47, D50 to D57, FY, POL, INV1, INV2 High-level input voltage Low-level input voltage Input leakage current 2) I/O pins PRSL, PLSR High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current VIH2 VIL2 VOH VOL ILI2 DVDD 0.3x DVDD 0.3x DVDD 10 V V V V A VIH1 VIL1 ILI1 DVDD 0.3x DVDD 10 V V A
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MN838850
I Electrical Characteristics (continued)
3. DC Characteristics at DVDD = 2.7 V to 3.6 V, AVDD = 14.5 V to 15.5 V, AVSS = DVSS = 0 V, Ta = -20 C to +75 C (continued) Parameter 3) Pull-down resistor pin TEST High-level input voltage Low-level input voltage Input leakage current Pull-down resistance VIH3 VIL3 ILI3 RPD 0.7 x DVDD 0 -10 40 100 DVDD 0.3x DVDD 10 350 V V A k Symbol Conditions Min Typ Max Unit
4) Reference voltage input pins VOPU, VOPL Input current 5) Analog output pins Y1 to Y384 Output current *4 IVOH IVOL Output voltage difference *5 VO VX = 15 V, VOUT = 14 V, AVDD = 15 V, DVDD = 3.3 V VX = 0.0 V, VOUT = 1.0 V, AVDD = 15 V, DVDD = 3.3 V AVDD = 15 V, DVDD = 3.3 V 0.2 AVSS+0.2 - 0.5 0.5 4 - 0.2 20 AVDD- 0.2 mV mA IVOP -100 100 A
6) Analog output pin (Y1 to Y384) output voltage range Operating voltage range *6 VO V
Note) 1. *1: The standard conditions are as follows. A clock frequency of 50 MHz, a raster period of 15 s, the data pattern fixed at FF, the POL level switched between high and low at each raster period, INV1 and INV2 held fixed at the low level, and each of VREF0 to VREF9 held fixed at its respective levels. *2: The maximum conditions are as follows. A clock frequency of 50 MHz, a raster period of 15 s, the data pattern switches between FF and 00 on each clock cycle, the POL level switched between high and low at each raster period, INV1 and INV2 held fixed at the low level, and each of VREF0 to VREF9 held fixed at its respective levels. *3: The loads on the analog output pins (Y1 to Y384) are shown below. The values of the components in the load circuit are subject to change.
AVDD DVDD ISS3 ISS4
ISS2 ISS1 A A
DUT AVDD DVDD DVSS Y1 Y2 * * * * * * * Y384 5 k 75 pF AVSS 75 pF AVSS
AVSS
0V
DUT : Device Under Test
*4: The VX are the output voltages from the analog output pins Y1 to Y384. The VOUT are the voltages applied to the analog output pins Y1 to Y384. *5: The standard conditions apply when the output voltages are at the same voltage as VOPL and VOPU. *6: Set up VREF0 to VREF9, VOPU, and VOPL so that the output voltages never exceed the output voltage range listed above. 2. The following formula expresses the power dissipation when the loads described in *3 above are attached. ISS1 x AVDD + ISS3 x DVDD Replace ISS1 in the above formula with the value of ISS2 to calculate the power dissipation when there is no load. 3. The supply current in the no load state is provided for reference purposes and is not guaranteed.
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I Electrical Characteristics (continued)
4. AC Characteristics at DVDD = 2.7 V to 3.6 V, AVDD = 14.5 V to 15.5 V, AVSS = DVSS = 0 V, Ta = -20 C to +75 C Parameter FY period Symbol tp twcH twcL tst1 thd1 tst2 thd2 twsL twsH td1 tc twA
*1
Conditions DVDD = 3.1 V to 3.6 V DVDD = 2.7 V to 3.6 V
Min 20 25 4 4 0 4 0 4 2 1
Typ 64
Max 13 17
Unit ns
Clock high-level period Clock low-level period Data and INV setup time Data and INV hold time Start pulse setup time Start pulse hold time Start pulse low-level period Start pulse high-level period Carry signal delay time
ns ns ns ns ns ns Clock cycles Clock cycles ns
CL = 15 pF, DVDD = 3.1 V to 3.6 V CL = 15 pF, DVDD = 2.7 V to 3.6 V

Carry signal rise time A signal low-level period A signal start pulse setup time Data input invalid time *1 Last data timing *1 LCD drive signal delay time *2,3
Clock cycles s Clock cycles Clock cycles 1 11 Clock cycles s
2 4
1
tst3 tng1 tng2 td2 AVDD = 15 V

Note) *1: The starting point is at the rise of the first clock cycle after the rise of the PRSL (PLSR) signal. *2: Stipulated as the value until the drive output voltage reaches the target output voltage 20 mV (not including the deviation). *3: See note 1. *3 in section 3. DC Characteristics for the analog output pin load.
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I Electrical Characteristics (continued)
4. AC Characteristics (continued)
tp FY tst Dxx INV1 INV2 Input PLSR(RL = "H") PRSL(RL = "L") Output PRSL(RL = "H") PLSR(RL = "L") twA A signal tst3 twsL tst2 VIH thd1
twcH
twcL
VIL
thd2
twsH
tc
td1 VOH
td2 Hi-Z Y1 to Y384 D/A converter setup period Target output voltage 20 mV (not including the deviation) Target output voltage
Hi-Z
The D/A converter setup period (when the outputs are high impedance) is synchronized with the falling edge of the A signal. Unless otherwise specified, the digital input and output levels are VIH = VOH 0.7 x DVDD, VIL = VOL = 0.3 x DVDD.
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I Electrical Characteristics (continued)
4. AC Characteristics (continued)
tng1 FY tst2 Input PLSR(RL = "H") PRSL(RL = "L") tst1 Dxx INV1 INV2 thd1 thd2
FY tng2 A singal tst1 Dxx INV1 INV2 Valid Valid Valid thd1 Invalid Invalid Invalid
Valid
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
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2001 MAR

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